1 cml semiconductor products product information FX009A features/applications 8 digitally controlled low-noise amplifiers 15 gain/attenuation steps 7 trimmers, with a 3db range in 0.43db steps 1 'volume' trimmer, with a 14db range in 2.0db steps brief description this product replaces the need for manual trimming of audible signals by using the host microprocessor to digitally control the set-up of all audio levels. applications include: (i) control, adjustment and set-up of communications equipment by an intelligent ate without manual intervention C eg. deviation, microphone and l/s level, rx audio level etc. (ii) automatic dynamic compensation of drift caused by variations in temperature, linearity, etc. (iii)fully automated servicing and re-alignment. the FX009A is a low-power, single 5-volt cmos device available in both 24-pin dil and smd package versions. the FX009A digitally adjustable amplifier array is intended to replace trimmer potentiometers and volume controls in cellular, pmr, telephony and communications applications where d.c., voice or data signals need adjustment. the FX009A is a low-noise single-chip lsi consisting eight digitally controlled amplifier stages, each with 15 distinct gain/attenuation steps. control of each individual amplifier is by an 8-bit serial data stream. seven of the amplifier stages offer a +/-3db range in steps of 0.43db, whilst the remaining amplifier offers a +/-14db range in steps of 2db, and is intended for volume control applications. each amplifier includes a 16th 'mute' state which sets the output to bias (v dd /2) and powersaves the entire section. minimum current drain may be achieved by muting all eight sections. publication d/009a/3 july 1994 low-noise digitally controlled amplifier array 8-bit serial data control output mute/powersave function audio and data gain control applications cellular, pmr, pabx applications FX009A fig.1 functional block diagram 8 - bit serial data input and line decoders 12345678 serial data input load/latch 1 2 3 4 8 7 6 16-line step controls to amplifiers 1 to 8 5 43 2 1 56 7 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 v dd v bias controlled audio output lines 8 - volume serial clock input load/latch v ss * output mute - powersave * * * * * * * v bias v bias v bias v bias v bias v bias v bias v bias 16
2 pin number function FX009A j 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 serial clock : this external clock pulse input is used to clock in the control data. see figure 4, data load timing. this input has an internal 1m w pullup resistor. load/latch : governs the loading and execution of the control data. during serial data loading this input should be kept at a logical '0' to ensure that data rippling past the latches has no effect. when all 8 bits have been loaded, this input should be strobed '0' t '1' t '0' to latch the new data in. data is executed on the falling edge of the strobe. if the load/latch input is used this pin should be left open circuit. this input has an internal 1m w pullup resistor. load/latch : the inverted load/latch input. this function governs the loading and execution of the control data. during serial data loading this input should be kept at a logical '1' to ensure that data rippling past the latches has no effect. when all 8 bits have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in. data is executed on the rising edge of the strobe. if the load/latch input is used this pin should be left open circuit. this input has an internal 1m w pulldown resistor. ch1 input : ch2 input : ch3 input : ch4 input : v bias : the output of the on-chip bias circuitry, held at v dd /2. this pin should be decoupled to v ss as shown in figure 2. ch5 input : ch6 input : ch7 input : ch8 input : v ss : negative supply rail (gnd). ch8 output : ch7 output : ch6 output : ch5 output : no internal connection. do not use. ch4 output : ch3 output : ch2 output : ch1 output : v dd : positive supply rail. a single +5-volt power supply is required. control data input : operation of the 8 amplifier channels (ch1 C ch8) is controlled by the 8 bits of data entered serially at this pin . the data is entered (bit 7 to bit 0) on the rising edge of the external serial clock. the data format is described in tables 1, 2 and figure 4. this input has an internal 1m w pullup resistor. analogue outputs : the individual "gain controlled" amplifier outputs. ch1 to ch7 range from -3db to +3db in 0.43db steps, ch8 could be utilized as a volume control, ranging from -14db to +14db in 2.0db steps. in the powersave mode the selected output is biased at v dd /2. analogue outputs note that amplifiers ch1 to ch8 are 'inverting amplifiers.' analogue inputs : these individual amplifier inputs are self-biasing, a.c. input analogue signals must be capacitively coupled to these pins, as shown in figure 2. in the powersave modes the inputs are biased at v dd /2. note that amplifiers ch1 to ch8 are 'inverting amplifiers.' analogue inputs : FX009A lg/ls 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
3 fig.3 sinad vs input level C typical values application notes application recommendations (f) analogue tracks should not run parallel to digital tracks. (g) a "ground plane" connected to v ss will assist in eliminating external pick-up on the channel input and output pins. (h) do not run high-level output tracks close to low- level input tracks. (i) input signal amplitudes should be applied with due regard to figure 3. (a) a noisy or badly regulated power supply can cause instability and/or variance of selected gains. (b) care should be taken on the design and layout of the printed circuit board. (c) all external components (figure 2) should be kept close to the FX009A package. (d) inputs and outputs should be screened wherever possible. (e) tracks should be kept short. to avoid excess noise and instability in the final installation it is recommended that the following points be noted. component unit value c 1 to c 8 0.1 m c 9 1.0 m c 10 1.0 m tolerances: c = 20% notes (1) channel amplifiers 1 to 8 are inverting amplifiers. (2) analogue input capacitors c 1 to c 8 are only required for a.c. input signals, d.c. input signals do not require these components. FX009A j - lg - ls serial clock input channel 1 input channel 2 input channel 3 input channel 4 input channel 5 input channel 6 input channel 7 input channel 8 input serial control data input c 3 c 5 load/latch load/latch channel 1 output channel 2 output channel 3 output channel 4 output x channel 5 output channel 6 output channel 7 output channel 8 output v ss v ss v bias v dd v dd c 1 c 2 c 4 c 6 c 7 c 8 c 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c 10 v ss fig.2 external component connections input level sinad (db) 30 40 50 60 -40 -30 -20 -10 0 input frequency = 1.0khz input level 0db ref: = 775mvrms ch1 to ch8 gain set to 0db 10.0 25.0 75.0 250.0 775.0 1000.0 1730.0 -17 110.0 db mvrms 7
4 serial data clock t pwl t pwh t ds loaded last logic '1' loaded first bit 7 bit 6 bit 1 bit 0 t dh serial data in (one 8-bit word) t llo 8th clock pulse next clock pulse t lld t llw load/latch load/latch fig.4 serial control data loading diagram data is loaded to the FX009A on the rising edge of the serial clock. loaded data is executed on the falling (rising) edge of the load/latch (load/latch) pulse. table 1 shows the format of each 4-bit address word, table 2 shows the format of each gain control word with figure 4 describing the data loading operation and timing. the gain of each amplifier block (channel 1 to channel 8) in the FX009A is set by a separate 8-bit data word ( bit 7 to bit 0 ). this 8-bit word, consisting of 4 address bits (bit 7 to bit 4) and 4 gain control bits (bit 3 to bit 0), is loaded to the control data input in serial format using the external data clock. table 1 address word format bit 7 bit 6 bit 5 bit 4 channel msb lsb selected 1000 1 1001 2 1010 3 1011 4 1100 5 1101 6 1110 7 1111 8 table 2 gain control word format bit 3 bit2 bit 1 bit 0 stage 1 to 7 stage 8 msb lsb (0.43db) (2.0db) 0000 powersave powersave 0001 -3.0 -14.0 db 0010 -2.571 -12.0 db 0011 -2.143 -10.0 db 0100 -1.714 -8.0 db 0101 -1.286 -6.0 db 0110 -0.857 -4.0 db 0111 -0.428 -2.0 db 1000 0 0db 1001 0.428 2.0 db 1010 0.857 4.0 db 1011 1.286 6.0 db 1100 1.714 8.0 db 1101 2.143 10.0 db 1110 2.571 12.0 db 1111 3.0 14.0 db data loading the 8-bit data word is loaded bit 7 first and bit 0 last. bit 7 must be a logic 1 to address the chip. if bit 7 in the word is a logic 0 that 8-bit word will not be executed. figure 4 (below) shows the timing information required to load and operate this device. t lld load/latch delay t llw load/latch pulse width t llo load/latch over time timing t pwh serial clock "high" pulse width t pwl serial clock "low" pulse width t ds data set-up time t dh data hold time
5 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation @ t amb 25 c 800mw max. derating 10mw/ c operating temperature range: FX009A j -30 c to +85 c (cerdip) FX009A lg/ls -30 c to +70 c (plastic) storage temperature range: FX009A j -55 c to +125 c (cerdip) FX009A lg/ls -40 c to +85 c (plastic) operating limits all device characteristics are measured under the following conditions unless otherwise specified: v dd = 5.0v, t amb = 25 c. audio level 0db ref: = 775mvrms. amplifier gain set = 0db. characteristics see note min. typ. max. unit static values supply voltage (v dd ) 4.5 5.0 5.5 v supply current C C all stages quiescent C 0.16 C ma C all stages operating C 3.75 C ma dynamic values control functions input logic '1' 3.5 C C v input logic '0' C C 1.5 v digital input impedances 0.5 1.0 C m w amplifier stages (general) bandwidth (-3db) 15.0 C C khz output impedance C 0.8 3.0 k w total harmonic distortion 1 C 0.35 0.5 % output noise level (per stage) 2 C 65.0 - m vrms onset of clipping 3 C 1.73 C vrms gain variation 4 C C 0.1 db interstage isolation C 60.0 C db trimmer stages (ch1 C ch7) gain -3.0 +3.0 db gain per step (15 in no.) C 0.43 C db step error 5 C C 0.2 db input impedance 100.0 C C k w volume stage (ch8) gain -14.0 +14.0 db gain per step (15 in no.) C 2.0 C db step error 5 C C 0.4 db input impedance 50.0 C C k w timing (figure 4) serial clock "high" pulse width (t pwh ) 250 C C ns serial clock "low" pulse width (t pwl ) 250 C C ns data set-up time (t ds ) 150 C C ns data hold time (t dh )50CCns load/latch over time (t llo ) C C 50.0 ns load/latch delay (t lld ) 200 C C ns load/latch pulse width (t llw ) 150 C C ns serial data clock frequency C C 2.0 mhz notes 1. gain set 0db, input level 1khz -3.0db (549mvrms). 2. a.c short-circuit input, measured in a 30khz bandwidth. 3. see figure 3. 4. over temperature and supply voltage range. 5. with reference to a 1.0khz signal.
6 package outlines the FX009A is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagrams and pins on all package styles number anti- clockwise when viewed from the top. handling precautions the FX009A is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. FX009Alg 24-pin quad plastic encapsulated bent and cropped (l1) FX009Aj 24-pin cerdip dil (j4) FX009Als 24-lead plastic leaded chip carrier (l2) cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. ordering information FX009Aj 24-pin cerdip dil (j4) FX009Alg 24-pin quad plastic encapsulated bent and cropped (l1) FX009Als 24-lead plastic leaded chip carrier (l2) not to scale max. body length 32.00mm max. body width 13.36mm not to scale max. body length 10.25mm max. body width 10.25mm not to scale max. body length 10.40mm max. body width 10.40mm
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